With the advent of multi-core processor, the clock rate of the processor may be adaptively adjusted according to the number of cores in use. When the number of cores in use is smaller, the processor could operate at a higher clock rate. Each core may access a portion of the dynamic random access memory (DRAM) for data storage. However, it is difficult for the DRAM to adjust its clock rate in accordance with the processor. Thus, even though the processing speed of the processor may increase due to few cores being in use, the overall performance bottleneck may be severely limited by the data access to the DRAM, as the gap of clock rates between the processor and the DRAM has been widened.